3 research outputs found
Efficient Placement and Migration Policies for an STT-RAM based Hybrid L1 Cache for Intermittently Powered Systems
The number of battery-powered devices is rapidly increasing due to the
widespread use of IoT-enabled nodes in various fields. Energy harvesters, which
help to power embedded devices, are a feasible alternative to replacing
battery-powered devices. In a capacitor, the energy harvester stores enough
energy to power up the embedded device and compute the task. This type of
computation is referred to as intermittent computing. Energy harvesters are
unable to supply continuous power to embedded devices. All registers and cache
in conventional processors are volatile. We require a Non-Volatile Memory
(NVM)-based Non-Volatile Processor (NVP) that can store registers and cache
contents during a power failure.
NVM-based caches reduce system performance and consume more energy than
SRAM-based caches. This paper proposes Efficient Placement and Migration
policies for hybrid cache architecture that uses SRAM and STT-RAM at the first
level cache. The proposed architecture includes cache block placement and
migration policies to reduce the number of writes to STT-RAM. During a power
failure, the backup strategy identifies and migrates the critical blocks from
SRAM to STT-RAM. When compared to the baseline architecture, the proposed
architecture reduces STT-RAM writes from 63.35% to 35.93%, resulting in a
32.85% performance gain and a 23.42% reduction in energy consumption. Our
backup strategy reduces backup time by 34.46% when compared to the baseline
An Efficient NVM based Architecture for Intermittent Computing under Energy Constraints
Battery-less technology evolved to replace battery technology. Non-volatile
memory (NVM) based processors were explored to store the program state during a
power failure. The energy stored in a capacitor is used for a backup during a
power failure. Since the size of a capacitor is fixed and limited, the
available energy in a capacitor is also limited and fixed. Thus, the capacitor
energy is insufficient to store the entire program state during frequent power
failures. This paper proposes an architecture that assures safe backup of
volatile contents during a power failure under energy constraints. Using a
proposed dirty block table (DBT) and writeback queue (WBQ), this work limits
the number of dirty blocks in the L1 cache at any given time. We further
conducted a set of experiments by varying the parameter sizes to help the user
make appropriate design decisions concerning their energy requirements. The
proposed architecture decreases energy consumption by 17.56%, the number of
writes to NVM by 18.97% at LLC, and 10.66% at a main-memory level compared to
baseline architecture
Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent Computing
Battery-less technology evolved to replace battery usage in space, deep
mines, and other environments to reduce cost and pollution. Non-volatile memory
(NVM) based processors were explored for saving the system state during a power
failure. Such devices have a small SRAM and large non-volatile memory. To make
the system energy efficient, we need to use SRAM efficiently. So we must select
some portions of the application and map them to either SRAM or FRAM. This
paper proposes an ILP-based memory mapping technique for Intermittently powered
IoT devices. Our proposed technique gives an optimal mapping choice that
reduces the system's Energy-Delay Product (EDP). We validated our system using
a TI-based MSP430FR6989 and MSP430F5529 development boards. Our proposed memory
configuration consumes 38.10% less EDP than the baseline configuration and
9.30% less EDP than the existing work under stable power. Our proposed
configuration achieves 15.97% less EDP than the baseline configuration and
21.99% less EDP than the existing work under unstable power. This work supports
intermittent computing and works efficiently during frequent power failures